Conventional EEPROM's employ 3 to 4 transistors. These include a tunnel diode device coupled to the floating gate of the sense transistor to charge the latter and a select or row transistor to activate the cell. The use of 3 or 4 transistors in a cell clearly limits the size reduction possible for EEPROM arrays. Moreover, since normal operation involves the application of voltages in excess of 15 volts current cells need special processing to reduce leakage and larger layout to avoid unwanted field transistor turn on. A high voltage applied to moats which constitute the sources and drains of the field effect transistors is a particularly serious problem due to the diffused nature of their formation. High voltages on such junctions lead to DC leakage currents, a need for greater moat-to-moat isolation spacing, and to bulk punchthrough. The row transistor is particularly vulnerable to the latter effects since high voltage is applied to its source during the ERASE mode.
High voltage requirements also obviously require high voltage transistors or level shifters in the column circuitry which are susceptible to a relatively high likelihood of failure. Finally, the presence of high voltages can result in unintended programming or reading of memory cells.
One solution to avoid such problems would be to lower the programming voltage by using thinner tunnel oxide of the order of 70 Angstroms thick. However, this solution would increase leakage thereby decreasing data retention. Coupling efficiency could also be increased but at the expensive of area.
It is therefore a principal object of this invention to provide an improved erasable electronically programmable memory cell. Another object is to provide a floating gate EEPROM which operates with lower voltages than current such devices. A further object is to provide an EEPROM cell which occupies a smaller area than current EEPROM devices.